Progressive miniaturization of feature sizes in circuit elements has improved the performance and increased the functional capability of integrated circuits (IC's). Back-end-of-line (BEOL) multilevel interconnect structures have been developed that complement advances in circuit element density realized by size reductions by more effectively routing signal paths between the constituent circuit elements of the IC. Circuit performance and functional capability of the circuit elements are eventually limited by the signal-transmission effectiveness and efficiency of the BEOL interconnect structure. Damascene processes are routinely used to fabricate such BEOL multilevel interconnect structures. In a single damascene process, vias are etched in a patterned layer of dielectric material and filled with metal to establish interlevel contacts with a lower conductor. The lower conductor may be the metallization lines of an underlying level of the interconnect structure. Trenches are then etched in another patterned layer of dielectric material and filled with metal to define intralevel metallization lines. In a dual-damascene process, trenches and vias are etched in a patterned layer of dielectric material and filled simultaneously by a single blanket deposition of metal. In single and dual-damascene processes, any excess overburden of metal on the dielectric layer is removed from the top of the structure in a planarization process, such as chemical mechanical polishing (CMP). Silicon oxide and fluorine-doped silicon glass (FSG) are common materials used to form the dielectric layer(s).
Increases in circuit element density as achieved by reducing the line-to-line spacings between adjacent, on-pitch metallization lines in each interconnect level and between metallization lines in adjacent interconnect levels. The reduction in line-to-line spacing serves to increase the line-to-line capacitance, which causes propagation delay by slowing the speed of the signals carried by the metallization lines, and results in cross talk noise. This increase in line-to-line capacitance may be offset by reducing the dielectric constant of the dielectric material constituting the dielectric layer(s). Conversely, a reduction in line-to-line capacitance by reducing the dielectric constant permits concomitant reductions in line-to-line spacing.
The reduction or elimination of these adverse capacitive couplings could advantageously lead to enhanced device speed and reduced power consumption. Consequently, a trend in interconnect structures is to form the dielectric layer from a dielectric material characterized by a relative permittivity or dielectric constant smaller than the dielectric constant of traditional materials. Candidate low-k materials include inorganic polymers, organic polymers such as polyamides and SiLK® from Dow Chemical Company, organo-inorganic materials like spin-on glasses, and silsesquioxane-based materials. Generally, these candidate low-k materials are characterized by a dielectric constant smaller than three (3).
Damascene processes place stringent requirements on the properties of the candidate low-k dielectric materials, which has limited the integration of low-k dielectrics into damascene processes. In particular, a suitable low-k dielectric material must have sufficient mechanical strength and adequate chemical stability to withstand the cleaning, etching, polishing, and thermal treatments imposed by damascene processing. After manufacture, BEOL interconnect structures formed using organic dielectric materials have experienced significant reliability problems resulting from mismatches in the thermal coefficient of expansion with neighboring inorganic materials.
What is needed, therefore, is a low-k dielectric material suitable for use in forming a structure in an integrated circuit, such as for use as a low-k dielectric layer in a BEOL interconnect structure for an integrated circuit, that is fully compatible with processes for forming such interconnect structures.